A phase change material typically refers to a chalcogenide material that has multiple crystalline states. Depending on a cooling rate from a liquid state, the chalcogenide material may form an amorphous chalcogenide glass or a chalcogenide crystal. The difference between the two states is physically characterized by presence or absence of a long range order. Further, the crystalline and amorphous states of the chalcogenide material have drastically different resistivity values. By manipulating the phase of the chalcogenide material, a binary data bit may be written into a phase change memory (PCM) device. By detecting the phase of the chalcogenide material, typically in the form of a resistivity measurement, the binary data bit stored in the PCM device may be read. Many types of PCM devices employing these methods are known in the art.
A typical chalcogenide material used in PCM devices is a germanium, antimony and tellurium compound commonly called GST (Ge2Se2Te5). Along with oxygen, sulfur, selenium, and polonium, tellurium belongs to the chalcogen group, hence the name chalcogenide material.
Referring to FIG. 1, a typical prior art phase change memory (PCM) element structure comprises a dielectric layer 10, a heater element 20, and a phase change material element 30. The phase change material element 30 comprises a phase changing portion 32 and a crystalline portion 34. The phase changing portion 32 is hemispherical. While both the phase changing portion 32 and the crystalline portion 34 comprise the same phase change material, only the state of the phase changing portion 32 switches between an amorphous state and a crystalline state, while the crystalline portion stays crystalline.
In a prior art PCM device as shown in FIG. 1, to change the state of the phase change material into an amorphous state, a high current is passed between the heater element 20 and the phase change element 30 causing the temperature of the heater element 20 to rise above the melting point of the phase change material. The phase changing portion 32, as shown in FIG. 1, melts to form a melt phase change material portion 32a as shown in FIG. 2(a). Typically, phase changing chalcogenide materials become liquid at a relatively high temperature, e.g., above 600° C. The time constant for cooling is less than 5 nanoseconds. Upon cooling, the melt phase change material portion 32a becomes an amorphous phase change material portion 32b as shown in FIG. 2(b).
A crystalline phase change material having a low resistivity value may be formed by raising the temperature of the phase change material to a crystallization temperature, which is typically around 300° C. and is below the melting temperature. Upon heating of the phase changing portion 32 above a recrystallization temperature but below the melting temperature, the phase changing portion 32 becomes a crystallized phase change material portion 32c as shown in FIG. 2(c) irrespective of its prior state, i.e., the prior state may have been a crystalline state or an amorphous state. Upon cooling, the crystallized phase change material portion 32c stays as the same crystallized phase change material portion 32c, i.e., the crystalline order of the phase change material is maintained.
As the power density of semiconductor devices increases in successive semiconductor technology generations with continued scaling of dimensions, the operational temperature of semiconductor devices increases. Precise characterization of local operational temperature of semiconductor devices becomes important in modeling the performance of semiconductor circuits. Further, real time monitoring of the temperature of semiconductor devices during operation allows controlled modulation of the operational frequency of semiconductor devices to help reduce heat-related performance degradation. For example, if a portion of a chip becomes excessively hot enough to cause a degradation of overall chip performance, a controller may instruct the portion of the circuit around the hot spot to operate at a lower frequency until the local temperature returns to a normal level.
In addition, some reliability test conditions subject a semiconductor chip to an elevated ambient temperature while operating the chip under the assumption that the combination of the internal heating from the chip operation and the ambient bias would provide a stress condition that accelerates degradation of the chip at a calculated pace. Such a reliability testing often assumes that the physical temperature within the chip under stress would be at an estimated temperature. However, the true temperature of the chip may vary locally depending on the power density during the chip operation, which is hard to estimate accurately, rendering an estimated local internal temperature subject to error. Thus, temperature profiling of a chip during chip operation provides valuable information that may be advantageously used to improve chip performance or to improve validity of chip testing under stress.
Precise measurement of internal local temperature of a chip is in general difficult to achieve. While temperature profiling circuits utilizing temperature dependence of the band gap width in semiconductor materials are known, the magnitude of change in the band gap is small, thus requiring a rather complicated and bulky sensing circuit. Other mechanisms for detecting local chip temperature are known, but most of them require a complex signal amplification circuitry and are prone to noise due to small magnitude of the signal from temperature detection elements.
Therefore, there exists a need for a structure and circuit that provides a strong temperature dependent signal and reliable temperature sensing, and methods of operating and manufacturing the same.